The present invention relates, generally, to a semiconductor device technique such as for the manufacture of a semiconductor integrated circuit device and, in particular, relates to a technique useful in the manufacture of a semiconductor device such as a semiconductor integrated circuit device to be applied to portable equipment, such as portable telephones and handy type personal computers, for which there is a strong trend toward reducing the size, the weight and the thickness of the product and, also, to such technique which leads to the manufacture of a relatively low cost semiconductor device such as a low cost semiconductor integrated circuit device package with improved seal properties in the package such as a CSP (Chip Size Package), although not limited thereto.
1. Recently, a trend toward reducing the size, the weight and the thickness of the product has become vigorous for electronic equipment along with an improved function and performance. This is largely due to a rapid increase in the use of personal equipment, such as personal telephones or handy type personal computers in recent years. Further, man-machine interface functions have been increased in personally manipulated equipment, for which easy handlability and operability have been considered increasingly important. It is considered that the trend will become more and more conspicuous in expected regular multimedia areas.
Under such circumstances, development for increasing the density and the degree of integration of semiconductor chips has progressed continuously; however, in addition to the size and the number of electrodes of the semiconductor chips being increased, the size of the packages have also increased rapidly. Accordingly, narrowing of the pitch of terminal leads has been promoted for facilitating the size reduction of the packages, which makes mounting of the package more difficult.
In view of the above, it has been proposed in recent years to provide high density packages with super-multiple pins having the same area as that of the semiconductor chips, and such packaging techniques are mentioned, for example, in various publications, such as “Nikkei Microdevices” p 98–p 102, issued on May 1, 1994, “Nikkei Microdevices” p 96–p 97, issued on Feb. 1, 1995 by Nikkei BP Co. and “Electronic Material”, p 22–p 28, issued on Apr. 1, 1995 (Heisei 7) by Kogyo Chosakai. One example of the structures produced with such packaging techniques, for example, as described in FIG. 6 of the “Electronic Material” publication, has a package structure in which a flexible wiring substrate is disposed by way of an elastomer (elastic material) on the surface of a semiconductor chip, leads on one end of wirings of the flexible wiring substrate are electrically connected with bonding pads on the surface of the semiconductor chip, and bump lands on the other end of the wirings of the flexible wiring substrate are electrically connected with the solder bumps.
The package structure has an outer size about equal to or greater than that of a semiconductor chip by the size of a protection frame optionally attached to the periphery of the chip, for which a flexible wiring substrate formed with solder bumps is used. The wiring pattern of the wiring substrate is made of a Cu foil having a Au plating on one side, the top ends of which to be connected with the pad of the chip constitute a lead pattern which is only composed of Au as a result of etching the Cu foil. In this structure, the flexible wiring substrate is bonded by an elastomer on the surface of the semiconductor chip and then the Au leads are connected with the bonding pads of the semiconductor chip.
2. A CSP, for example, which is a thin, compact semiconductor device of chip size, is often used in printed circuit boards built into portable electronic devices such as that referred-to above. The general structure of a CSP comprises a thin film wiring substrate on which are mounted bump electrodes which are external terminals, leads electrically connected to electrode pads of a semiconductor chip, an elastomer (elastic structure/elastic structural material) arranged between the semiconductor chip and the thin film wiring substrate and having approximately the same size as the thin film wiring substrate, and sealing parts which seal the electrode pads and the leads of the thin film wiring substrate connected to it.
Structures of CSPs studied by the inventors for comparison purposes, also, are described, for example, in “Nikkei Microdevices” Apr. 1, 1997, No. 142, pp. 44–53, published by Nikkei BP Co. on Apr. 1, 1997, and, in particular, the next generation CSP structure (comparison examples) described in FIG. 6, on page 48 thereof. This CSP comprises a semiconductor chip having electrode pads formed on its main surface, bump electrodes which are external terminals over the main surface of the semiconductor chip, and a contour ring outside the semiconductor chip.